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DM74AS161 * DM74AS163 Synchronous 4-Bit Counter with Asynchronous Clear * Synchronous 4-Bit Counter
April 1984 Revised March 2000
DM74AS161 * DM74AS163 Synchronous 4-Bit Counter with Asynchronous Clear * Synchronous 4-Bit Counter
General Description
These synchronous presettable counters feature an internal carry look ahead for application in high speed counting designs. The DM74AS161 and DM74AS163 are 4-bit binary counters. The DM74AS161 clear asynchronously, while the DM74AS163 clear synchronously. The carry output is decoded to prevent spikes during normal counting mode of operation. Synchronous operation is provided by having all flip-flops clocked simultaneously so that outputs change coincident with each other when so instructed by count enable inputs and internal gating. This mode of operation eliminates the output counting spikes which are normally associated with asynchronous (ripple clock) counters. A buffered clock input triggers the four flip-flops on the rising (positive-going) edge of the clock input waveform. These counters are fully programmable, that is, the outputs may each be preset to either level. As presetting is synchronous, setting up a low level at the LOAD input disables the counter and causes the outputs to agree with set up data after the next clock pulse regardless of the levels of enable input. LOW-to-HIGH transitions at the LOAD input are perfectly acceptable regardless of the logic levels on the clock or enable inputs. The DM74AS161 clear function is asynchronous. A low level at the clear input sets all four of the flip-flop outputs LOW regardless of the levels of clock, load or enable inputs. This counter is provided with a clear on power-up feature. The DM74AS163 clear function is synchronous; and a low level at the clear input sets all four of the flip-flop outputs LOW after the next clock pulse, regardless of the levels of enable inputs. This synchronous clear allows the count length to be modified easily, as decoding the maximum count desired can be accomplished with one external NAND gate. The gate output is connected to the clear input to synchronously clear the counter to all LOW outputs. LOW-to-HIGH transitions at the clear input of the DM74AS163 is also permissible regardless of the levels of logic on the clock, enable or load inputs. The carry look ahead circuitry provides for cascading counters for n bit synchronous application without additional gating. Instrumental in accomplishing this function are two count-enable inputs (P and T) and a ripple carry output. Both count-enable inputs must be HIGH to count. The T input is fed forward to enable the ripple carry output. The ripple carry output thus enabled will produce a high level output pulse with a duration approximately equal to the high level portion of QA output. This high level overflow ripple carry pulse can be used to enable successive cascaded stages. HIGH-to-LOW level transitions at the enable P or T inputs of the DM74AS161 and DM74AS163, may occur regardless of the logic level on the clock. The DM74AS161 and DM74AS163 feature a fully independent clock circuit. Changes made to control inputs (enable P or T, or load) that will modify the operating mode will have no effect until clocking occurs. The function of the counter (whether enabled, disabled, loading or counting) will be dictated solely by the conditions meeting the stable set-up and hold times.
Features
s Switching specifications at 50 pF s Switching specifications guaranteed over full temperature and VCC range s Advanced oxide-isolated, ion-implanted Schottky TTL process s Functionally and pin-for-pin compatible with Schottky and low power Schottky TTL counterpart s Improved AC performance over Schottky and low power Schottky counterparts s Synchronously programmable s Internal look ahead for fast counting s Carry output for n-bit cascading s Synchronous counting s Load control line s ESD inputs
Ordering Code:
Order Number DM74AS161M DM74AS161N DM74AS163M DM74AS163N Package Number M16A N16E M16A N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
(c) 2000 Fairchild Semiconductor Corporation
DS006291
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DM74AS161 * DM74AS163
Connection Diagram
Logic Diagrams
DM74AS161
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DM74AS161 * DM74AS163
DM74AS163
3
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DM74AS161 * DM74AS163
Absolute Maximum Ratings(Note 1)
Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range Typical JA N Package M Package 71.5C/W 101.0C/W 7V 7V 0C to +70C -65C to +150C
Note 1: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation.
Recommended Operating Conditions
Symbol VCC VIH VIL IOH IOL fCLK tSU Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Clock Frequency tSETUP, Set-Up Time Data; A, B, C, D En P, En T LOAD CLEAR (Only for DM74AS163) Set-up 1 (Only for DM74AS161) tH tHOLD, Hold Time Data; A, B, C, D En P, En T LOAD CLEAR (Only for DM74AS163) Hold 0 (Only for DM74AS161) tWCLK tWCLR Width of Clock Pulse Width of Clear Pulse, (DM74ASAS161 LOW) 6.7 8 ns ns CLEAR 0 0 0 0 0 ns ns ns ns ns CLEAR LOW HIGH 0 8 8 8 12 9 8 Parameter Min 4.5 2 0.8 -2 20 75 Nom 5 Max 5.5 Units V V V mA mA MHz ns ns ns ns ns
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DM74AS161 * DM74AS163
Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at VCC = 5V, TA = 25C Symbol VIK VOH VOL II Parameter Input Clamp Voltage HIGH Level Output Voltage LOW Level Output Voltage Input Current @ Max Input Voltage IOH = -2 mA, VCC = 4.5 to 5.5V VCC = 4.5V, IOL = 20 mA VCC = 5.5V, VIH = 7V VCC = 5.5V, VIH = 2.7V IIL LOW Level Input Current VCC = 5.5V, VIL = 0.4V IO (Note 2) ICC Output Drive Current Supply Current VCC = 5.5V, VO = 2.25V VCC = 5.5V LOAD ENT Others IIH HIGH Level Input Current LOAD ENT Others LOAD ENT Others -30 35 Conditions VCC = 4.5V, II = -18 mA VCC - 2 0.35 0.5 0.3 0.2 0.1 60 40 20 -0.5 -1 -0.5 -112 53 mA mA mA A mA Min Typ Max -1.2 Units V V V
Note 2: The output conditions have been chosen to produce a current that closely approximates one half of the true short circuit output current, I OS.
Switching Characteristics
over recommended operating free air temperature range Symbol fMAX tPHL tPLH Parameter Maximum Clock Frequency Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output with Load HIGH tPLH Propagation Delay Time LOW-to-HIGH Level Output with Load LOW tPLH tPHL tPLH tPHL tPHL Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time HIGH-to-LOW Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output Clock Clock En T En T CLEAR (DM74AS161) CLEAR (DM74AS161) Any Q Any Q Ripple Carry Ripple Carry 1 2 1.5 1 7 13 9 8.5 ns ns ns ns Clock Ripple Carry 3 16.5 ns Clock Ripple Carry 1 8 ns Conditions VCC = 4.5V to 5.5V RL = 500 CL = 50 pF Clock Ripple Carry From To Min 75 2 12.5 Max Units MHz ns
Any Q
2
13
ns
Ripple Carry
2
12.5
ns
5
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DM74AS161 * DM74AS163
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A
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DM74AS161 * DM74AS163 Synchronous 4-Bit Counter with Asynchronous Clear * Synchronous 4-Bit Counter
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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